Acronym for Reduced Instruction Set Computing. A microprocessor design that focuses on rapid and efficient processing of a relatively small set of simple instructions that comprises most of the instructions a computer decodes and executes. RISC architecture optimizes each of these instructions so that it can be carried out very rapidly—usually within a single clock cycle. RISC chips thus execute simple instructions more quickly than general-purpose CISC (Complex Instruction Set Computing) microprocessors, which are designed to handle a much wider array of instructions. They are, however, slower than CISC chips at executing complex instructions, which must be broken down into many machine instructions that RISC microprocessors can perform. Families of RISC chips include Sun Microsystems’ SPARC, Motorola’s 88000, Intel’s i860, and the PowerPC developed by Apple, IBM, and Motorola. See also architecture, SPARC. Compare CISC.
(acronym for reduced instruction-set computer) In computing, a microprocessor (processor on a single chip) that carries out fewer instructions than other (CISC) microprocessors in common use in the 1990s. Because of the low number of machine code instructions, the processor carries out those instructions very quickly.
Računar koji radi veoma brzo jer njegov mikroprocesor može da izvršava samo ograničen skup naredbi. Ideja je bila da, pošto se od tih malih stvari prave veće stvari, ograničen broj naredbi ne guši RISC procesor.